FPGA Archives - Page 7 of 9

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Low‑power half‑select free single‑ended 10 transistor SRAM cell
₹5,500.00

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LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
₹5,500.00

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Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology
₹5,500.00

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Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells
₹4,500.00

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Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
₹4,500.00

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Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
₹4,500.00

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Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter
₹5,500.00

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Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs
₹5,500.00

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OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
₹4,500.00

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Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
₹5,500.00

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Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation
₹4,500.00

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Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications
₹5,500.00

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Low‑power half‑select free single‑ended 10 transistor SRAM cell

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications

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Low‑power half‑select free single‑ended 10 transistor SRAM cell

Share on:

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Share on:

Modeling and Design of EMI-Immune OpAmps in 0.18-μ m CMOS Technology

Share on:

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

Share on:

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

Share on:

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Share on:

Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

Share on:

Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs

Share on:

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

Share on:

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Share on:

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

Share on:

Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications

Share on:

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